module mux( input [15:0] r0,
            input [15:0] r1,
            input [15:0] r2,
            input [15:0] r3,
            input [15:0] r4,
            input [15:0] r5,
            input [15:0] r6,
            input [15:0] r7,
            input [15:0] imediate,
            input [15:0] R,
            input [9:0] one_hot_sel,
            output reg [15:0] out);

always@(*) begin
    out = 16'bz; //default assignment para evitar X
    case(one_hot_sel)
        10'b0000000001 : out = r0;
        10'b0000000010 : out = r1;
        10'b0000000100 : out = r2;
        10'b0000001000 : out = r3;
        10'b0000010000 : out = r4;
        10'b0000100000 : out = r5;
        10'b0001000000 : out = r6;
        10'b0010000000 : out = r7;
        10'b0100000000 : out = imediate;
        10'b1000000000 : out = R;
    endcase
end

endmodule        





